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Searched refs:mmJPEG_CGC_GATE (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Djpeg_v3_0.c228 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v3_0_disable_clock_gating()
234 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v3_0_disable_clock_gating()
248 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v3_0_enable_clock_gating()
254 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v3_0_enable_clock_gating()
Djpeg_v2_5.c262 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_disable_clock_gating()
267 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); in jpeg_v2_5_disable_clock_gating()
281 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_enable_clock_gating()
287 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); in jpeg_v2_5_enable_clock_gating()
Djpeg_v2_0.c293 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v2_0_disable_clock_gating()
299 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v2_0_disable_clock_gating()
316 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v2_0_enable_clock_gating()
322 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v2_0_enable_clock_gating()
Dvcn_v1_0.c465 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_disable_clock_gating()
467 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
590 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_enable_clock_gating()
592 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); in vcn_v1_0_enable_clock_gating()
654 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_offset.h138 #define mmJPEG_CGC_GATE … macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h298 #define mmJPEG_CGC_GATE … macro
Dvcn_2_5_offset.h363 #define mmJPEG_CGC_GATE … macro
Dvcn_2_0_0_offset.h348 #define mmJPEG_CGC_GATE … macro
Dvcn_3_0_0_offset.h631 #define mmJPEG_CGC_GATE … macro