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Searched refs:mmMC_SEQ_TIMER_WR (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_d.h961 #define mmMC_SEQ_TIMER_WR 0x0AC9 macro
Dgmc_7_1_d.h848 #define mmMC_SEQ_TIMER_WR 0xac9 macro
Dgmc_8_1_d.h952 #define mmMC_SEQ_TIMER_WR 0xac9 macro