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Searched refs:mmMP0_SMN_C2PMSG_42_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/mp/
Dmp_12_0_0_offset.h49 #define mmMP0_SMN_C2PMSG_42_BASE_IDX … macro
Dmp_10_0_offset.h49 #define mmMP0_SMN_C2PMSG_42_BASE_IDX … macro
Dmp_9_0_offset.h49 #define mmMP0_SMN_C2PMSG_42_BASE_IDX 0 macro
Dmp_11_0_offset.h49 #define mmMP0_SMN_C2PMSG_42_BASE_IDX … macro