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Searched refs:mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/mp/
Dmp_9_0_offset.h339 #define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0 macro
Dmp_11_0_offset.h329 #define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX macro