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Searched refs:mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_offset.h2281 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX … macro
Dnbio_7_0_offset.h4163 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX … macro
Dnbio_7_4_offset.h2601 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX … macro
Dnbio_2_3_offset.h249 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX … macro