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Searched refs:mmRLC_SRM_CNTL_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6142 #define mmRLC_SRM_CNTL_BASE_IDX … macro
Dgc_9_1_offset.h6364 #define mmRLC_SRM_CNTL_BASE_IDX … macro
Dgc_9_2_1_offset.h6340 #define mmRLC_SRM_CNTL_BASE_IDX … macro
Dgc_10_1_0_offset.h9456 #define mmRLC_SRM_CNTL_BASE_IDX … macro
Dgc_10_3_0_offset.h9282 #define mmRLC_SRM_CNTL_BASE_IDX … macro