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Searched refs:mmSCRATCH_REG1 (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_offset.h215 #define mmSCRATCH_REG1 … macro
Dgc_9_0_offset.h4643 #define mmSCRATCH_REG1 … macro
Dgc_9_1_offset.h4873 #define mmSCRATCH_REG1 … macro
Dgc_9_2_1_offset.h4829 #define mmSCRATCH_REG1 … macro
Dgc_10_1_0_offset.h7107 #define mmSCRATCH_REG1 … macro
Dgc_10_3_0_offset.h6730 #define mmSCRATCH_REG1 … macro
/drivers/gpu/drm/amd/amdgpu/
Dsoc15_common.h85 uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \
Dgfx_v9_0.c750 …ch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; in gfx_v9_0_rlcg_wreg()
Dgfx_v10_0.c1380 …ch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; in gfx_v10_rlcg_wreg()
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1182 #define mmSCRATCH_REG1 0x2141 macro
Dgfx_7_0_d.h405 #define mmSCRATCH_REG1 0xc041 macro
Dgfx_7_2_d.h417 #define mmSCRATCH_REG1 0xc041 macro
Dgfx_8_1_d.h455 #define mmSCRATCH_REG1 0xc041 macro
Dgfx_8_0_d.h455 #define mmSCRATCH_REG1 0xc041 macro