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Searched refs:mmSDMA0_PERFMON_CNTL_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h185 #define mmSDMA0_PERFMON_CNTL_BASE_IDX … macro
Dsdma0_4_0_offset.h189 #define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 macro
Dsdma0_4_2_2_offset.h189 #define mmSDMA0_PERFMON_CNTL_BASE_IDX … macro
Dsdma0_4_2_offset.h187 #define mmSDMA0_PERFMON_CNTL_BASE_IDX … macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h156 #define mmSDMA0_PERFMON_CNTL_BASE_IDX … macro