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Searched refs:mmSDMA0_UTCL1_WR_STATUS (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h138 #define mmSDMA0_UTCL1_WR_STATUS … macro
Dsdma0_4_0_offset.h140 #define mmSDMA0_UTCL1_WR_STATUS 0x003f macro
Dsdma0_4_2_2_offset.h140 #define mmSDMA0_UTCL1_WR_STATUS … macro
Dsdma0_4_2_offset.h140 #define mmSDMA0_UTCL1_WR_STATUS … macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h115 #define mmSDMA0_UTCL1_WR_STATUS … macro
Dgc_10_3_0_offset.h112 #define mmSDMA0_UTCL1_WR_STATUS … macro