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Searched refs:mmSDMA1_RLC0_IB_CNTL (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c111 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
251 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
Dsdma_v3_0.c90 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
108 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
128 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
142 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
158 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
Dsdma_v4_0.c108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h333 #define mmSDMA1_RLC0_IB_CNTL 0x370a macro
Doss_3_0_1_d.h434 #define mmSDMA1_RLC0_IB_CNTL 0x370a macro
Doss_2_0_d.h369 #define mmSDMA1_RLC0_IB_CNTL 0x370a macro
Doss_3_0_d.h535 #define mmSDMA1_RLC0_IB_CNTL 0x370a macro
/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_0_offset.h390 #define mmSDMA1_RLC0_IB_CNTL 0x014a macro
Dsdma1_4_2_offset.h386 #define mmSDMA1_RLC0_IB_CNTL macro
Dsdma1_4_2_2_offset.h390 #define mmSDMA1_RLC0_IB_CNTL macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h1389 #define mmSDMA1_RLC0_IB_CNTL macro
Dgc_10_3_0_offset.h1428 #define mmSDMA1_RLC0_IB_CNTL macro