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Searched refs:mmSDMA3_RLC1_RB_WPTR (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/sdma3/
Dsdma3_4_2_2_offset.h464 #define mmSDMA3_RLC1_RB_WPTR … macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_3_0_offset.h11931 #define mmSDMA3_RLC1_RB_WPTR … macro