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Searched refs:mmSQ_CONFIG (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1413 #define mmSQ_CONFIG 0x2300 macro
Dgfx_7_0_d.h1785 #define mmSQ_CONFIG 0x2300 macro
Dgfx_7_2_d.h1806 #define mmSQ_CONFIG 0x2300 macro
Dgfx_8_1_d.h1967 #define mmSQ_CONFIG 0x2300 macro
Dgfx_8_0_d.h1999 #define mmSQ_CONFIG 0x2300 macro
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c1997 WREG32(mmSQ_CONFIG, 1); in gfx_v7_0_constants_init()
2025 WREG32(mmSQ_CONFIG, 0); in gfx_v7_0_constants_init()
Dgfx_v8_0.c319 mmSQ_CONFIG, 0x07f80000, 0x01180000,
350 mmSQ_CONFIG, 0x07f80000, 0x01180000,
382 mmSQ_CONFIG, 0x07f80000, 0x07180000,
Dgfx_v9_0.c705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
2554 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); in gfx_v9_0_init_sq_config()
2557 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); in gfx_v9_0_init_sq_config()
Dgfx_v6_0.c1752 WREG32(mmSQ_CONFIG, 0); in gfx_v6_0_constants_init()
Dgfx_v10_0.c3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h393 #define mmSQ_CONFIG macro
Dgc_9_1_offset.h387 #define mmSQ_CONFIG macro
Dgc_9_2_1_offset.h383 #define mmSQ_CONFIG macro
Dgc_10_1_0_offset.h2427 #define mmSQ_CONFIG macro
Dgc_10_3_0_offset.h2514 #define mmSQ_CONFIG macro