| /drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v5_0.c | 605 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
643 WREG32(mmUVD_CGC_GATE, data3); in uvd_v5_0_enable_clock_gating()
698 data = RREG32(mmUVD_CGC_GATE);
729 WREG32(mmUVD_CGC_GATE, data);
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| D | uvd_v6_0.c | 622 data = RREG32(mmUVD_CGC_GATE);
690 WREG32(mmUVD_CGC_GATE, data);
1256 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1303 WREG32(mmUVD_CGC_GATE, data3); in uvd_v6_0_enable_clock_gating()
1359 data = RREG32(mmUVD_CGC_GATE);
1392 WREG32(mmUVD_CGC_GATE, data);
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| D | vcn_v2_5.c | 569 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
591 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); in vcn_v2_5_disable_clock_gating()
593 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v2_5_disable_clock_gating()
698 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
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| D | vcn_v3_0.c | 666 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); in vcn_v3_0_disable_clock_gating()
688 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); in vcn_v3_0_disable_clock_gating()
690 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v3_0_disable_clock_gating()
817 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
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| D | uvd_v7_0.c | 1632 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1641 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1674 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
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| D | vcn_v1_0.c | 480 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
501 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
686 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
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| D | uvd_v3_1.c | 330 WREG32(mmUVD_CGC_GATE, 0); in uvd_v3_1_start()
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| D | uvd_v4_2.c | 266 WREG32(mmUVD_CGC_GATE, 0); in uvd_v4_2_start()
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| D | vcn_v2_0.c | 505 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
526 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
630 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
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| D | si.c | 110 mmUVD_CGC_GATE, 0x00000008, 0x00000000,
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| /drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 35 #define mmUVD_CGC_GATE 0x3D2A macro
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| D | uvd_4_2_d.h | 42 #define mmUVD_CGC_GATE 0x3d2a macro
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| D | uvd_3_1_d.h | 42 #define mmUVD_CGC_GATE 0x3d2a macro
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| D | uvd_5_0_d.h | 48 #define mmUVD_CGC_GATE 0x3d2a macro
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| D | uvd_6_0_d.h | 64 #define mmUVD_CGC_GATE 0x3d2a macro
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| D | uvd_7_0_offset.h | 144 #define mmUVD_CGC_GATE … macro
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| /drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 304 #define mmUVD_CGC_GATE … macro
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| D | vcn_2_5_offset.h | 497 #define mmUVD_CGC_GATE … macro
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| D | vcn_2_0_0_offset.h | 504 #define mmUVD_CGC_GATE … macro
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| D | vcn_3_0_0_offset.h | 813 #define mmUVD_CGC_GATE … macro
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