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Searched refs:mmUVD_CTX_DATA (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h39 #define mmUVD_CTX_DATA 0x3D29 macro
Duvd_4_2_d.h41 #define mmUVD_CTX_DATA 0x3d29 macro
Duvd_3_1_d.h41 #define mmUVD_CTX_DATA 0x3d29 macro
Duvd_5_0_d.h47 #define mmUVD_CTX_DATA 0x3d29 macro
Duvd_6_0_d.h63 #define mmUVD_CTX_DATA 0x3d29 macro
Duvd_7_0_offset.h142 #define mmUVD_CTX_DATA macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h302 #define mmUVD_CTX_DATA macro
Dvcn_2_5_offset.h605 #define mmUVD_CTX_DATA macro
Dvcn_2_0_0_offset.h502 #define mmUVD_CTX_DATA macro
Dvcn_3_0_0_offset.h941 #define mmUVD_CTX_DATA macro
/drivers/gpu/drm/amd/amdgpu/
Dcik.c130 r = RREG32(mmUVD_CTX_DATA); in cik_uvd_ctx_rreg()
141 WREG32(mmUVD_CTX_DATA, (v)); in cik_uvd_ctx_wreg()
Dsoc15.c146 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); in soc15_uvd_ctx_rreg()
160 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); in soc15_uvd_ctx_wreg()
Dvi.c165 r = RREG32(mmUVD_CTX_DATA); in vi_uvd_ctx_rreg()
176 WREG32(mmUVD_CTX_DATA, (v)); in vi_uvd_ctx_wreg()
Dsi.c987 r = RREG32(mmUVD_CTX_DATA); in si_uvd_ctx_rreg()
998 WREG32(mmUVD_CTX_DATA, (v)); in si_uvd_ctx_wreg()