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Searched refs:mmUVD_DPG_LMA_DATA (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Damdgpu_vcn.h77 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
82 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
130 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
136 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value); \
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h38 #define mmUVD_DPG_LMA_DATA macro
Dvcn_2_5_offset.h411 #define mmUVD_DPG_LMA_DATA macro
Dvcn_2_0_0_offset.h396 #define mmUVD_DPG_LMA_DATA macro
Dvcn_3_0_0_offset.h687 #define mmUVD_DPG_LMA_DATA macro