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Searched refs:mmUVD_DPG_LMA_MASK (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Damdgpu_vcn.h71 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h40 #define mmUVD_DPG_LMA_MASK … macro
Dvcn_2_5_offset.h413 #define mmUVD_DPG_LMA_MASK … macro
Dvcn_2_0_0_offset.h398 #define mmUVD_DPG_LMA_MASK … macro
Dvcn_3_0_0_offset.h689 #define mmUVD_DPG_LMA_MASK … macro