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Searched refs:mmUVD_DPG_PAUSE (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c1225 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & in vcn_v1_0_pause_dpg_mode()
1239 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v1_0_pause_dpg_mode()
1240 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v1_0_pause_dpg_mode()
1269 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v1_0_pause_dpg_mode()
1281 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & in vcn_v1_0_pause_dpg_mode()
1300 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v1_0_pause_dpg_mode()
1301 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v1_0_pause_dpg_mode()
1330 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v1_0_pause_dpg_mode()
Dvcn_v2_5.c1411 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & in vcn_v2_5_pause_dpg_mode()
1423 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_5_pause_dpg_mode()
1426 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v2_5_pause_dpg_mode()
1465 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_5_pause_dpg_mode()
Dvcn_v2_0.c1211 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & in vcn_v2_0_pause_dpg_mode()
1222 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_0_pause_dpg_mode()
1225 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v2_0_pause_dpg_mode()
1269 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_0_pause_dpg_mode()
Dvcn_v3_0.c1547 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & in vcn_v3_0_pause_dpg_mode()
1557 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v3_0_pause_dpg_mode()
1560 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v3_0_pause_dpg_mode()
1596 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v3_0_pause_dpg_mode()
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h42 #define mmUVD_DPG_PAUSE … macro
Dvcn_2_5_offset.h415 #define mmUVD_DPG_PAUSE … macro
Dvcn_2_0_0_offset.h400 #define mmUVD_DPG_PAUSE … macro
Dvcn_3_0_0_offset.h691 #define mmUVD_DPG_PAUSE … macro