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Searched refs:mmUVD_GP_SCRATCH5 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h320 #define mmUVD_GP_SCRATCH5 … macro
Dvcn_2_5_offset.h643 #define mmUVD_GP_SCRATCH5 … macro
Dvcn_2_0_0_offset.h528 #define mmUVD_GP_SCRATCH5 … macro
Dvcn_3_0_0_offset.h993 #define mmUVD_GP_SCRATCH5 … macro