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Searched refs:mmUVD_JRBC_RB_CNTL (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Djpeg_v1_0.c78 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring()
90 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring()
123 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring()
523 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | in jpeg_v1_0_start()
529 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); in jpeg_v1_0_start()
Djpeg_v3_0.c353 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v3_0_start()
360 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v3_0_start()
Djpeg_v2_5.c330 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v2_5_start()
337 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v2_5_start()
Djpeg_v2_0.c360 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v2_0_start()
367 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v2_0_start()
Dvcn_v1_0.c1308 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, in vcn_v1_0_pause_dpg_mode()
1317 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, in vcn_v1_0_pause_dpg_mode()
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h264 #define mmUVD_JRBC_RB_CNTL … macro
Dvcn_2_5_offset.h139 #define mmUVD_JRBC_RB_CNTL … macro
Dvcn_2_0_0_offset.h124 #define mmUVD_JRBC_RB_CNTL … macro
Dvcn_3_0_0_offset.h337 #define mmUVD_JRBC_RB_CNTL … macro