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Searched refs:mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h281 #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … macro
Dvcn_2_5_offset.h148 #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … macro
Dvcn_2_0_0_offset.h133 #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … macro
Dvcn_3_0_0_offset.h346 #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX … macro