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Searched refs:mmUVD_JRBC_RB_WPTR (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Djpeg_v3_0.c359 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v3_0_start()
362 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v3_0_start()
424 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v3_0_dec_ring_get_wptr()
442 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v3_0_dec_ring_set_wptr()
Djpeg_v2_5.c336 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v2_5_start()
339 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_start()
404 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_dec_ring_get_wptr()
422 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_5_dec_ring_set_wptr()
Djpeg_v1_0.c154 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v1_0_decode_ring_get_wptr()
168 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v1_0_decode_ring_set_wptr()
528 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v1_0_start()
533 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v1_0_start()
Djpeg_v2_0.c366 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v2_0_start()
369 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_start()
432 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_dec_ring_get_wptr()
450 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
Dvcn_v1_0.c1181 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); in vcn_v1_0_stop_dpg_mode()
1316 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); in vcn_v1_0_pause_dpg_mode()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_offset.h126 #define mmUVD_JRBC_RB_WPTR … macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h262 #define mmUVD_JRBC_RB_WPTR … macro
Dvcn_2_5_offset.h137 #define mmUVD_JRBC_RB_WPTR … macro
Dvcn_2_0_0_offset.h122 #define mmUVD_JRBC_RB_WPTR … macro
Dvcn_3_0_0_offset.h335 #define mmUVD_JRBC_RB_WPTR … macro