| /drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 47 #define mmUVD_LMI_CTRL 0x3D66 macro
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| D | uvd_4_2_d.h | 49 #define mmUVD_LMI_CTRL 0x3d66 macro
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| D | uvd_3_1_d.h | 51 #define mmUVD_LMI_CTRL 0x3d66 macro
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| D | uvd_5_0_d.h | 55 #define mmUVD_LMI_CTRL 0x3d66 macro
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| D | uvd_6_0_d.h | 71 #define mmUVD_LMI_CTRL 0x3d66 macro
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| D | uvd_7_0_offset.h | 158 #define mmUVD_LMI_CTRL … macro
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| /drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 336 #define mmUVD_LMI_CTRL … macro
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| D | vcn_2_5_offset.h | 959 #define mmUVD_LMI_CTRL … macro
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| D | vcn_2_0_0_offset.h | 562 #define mmUVD_LMI_CTRL … macro
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| D | vcn_3_0_0_offset.h | 1473 #define mmUVD_LMI_CTRL … macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v1_0.c | 811 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); in vcn_v1_0_start_spg_mode()
812 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | in vcn_v1_0_start_spg_mode()
993 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, in vcn_v1_0_start_dpg_mode()
1048 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, in vcn_v1_0_start_dpg_mode()
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| D | uvd_v3_1.c | 351 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | in uvd_v3_1_start()
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| D | uvd_v4_2.c | 286 WREG32(mmUVD_LMI_CTRL, 0x203108); in uvd_v4_2_start()
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| D | vcn_v2_5.c | 813 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
959 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); in vcn_v2_5_start()
961 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8| in vcn_v2_5_start()
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| D | vcn_v2_0.c | 835 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v2_0_start_dpg_mode()
963 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); in vcn_v2_0_start()
964 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | in vcn_v2_0_start()
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| D | vcn_v3_0.c | 937 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
1087 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); in vcn_v3_0_start()
1088 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | in vcn_v3_0_start()
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| D | uvd_v5_0.c | 327 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | in uvd_v5_0_start()
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| D | uvd_v7_0.c | 867 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), in uvd_v7_0_sriov_start()
982 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL, in uvd_v7_0_start()
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| D | uvd_v6_0.c | 743 WREG32(mmUVD_LMI_CTRL, in uvd_v6_0_start()
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