| /drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v5_0.c | 311 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_start()
353 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_start()
437 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_stop()
448 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_stop()
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| D | uvd_v7_0.c | 851 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_sriov_start()
908 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_sriov_start()
964 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), in uvd_v7_0_start()
1015 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, in uvd_v7_0_start()
1127 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_stop()
1141 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, in uvd_v7_0_stop()
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| D | uvd_v3_1.c | 368 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v3_1_start()
473 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v3_1_stop()
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| D | uvd_v4_2.c | 304 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start()
409 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v4_2_stop()
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| D | vcn_v2_5.c | 848 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
1007 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start()
1359 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v2_5_stop()
1361 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v2_5_stop()
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| D | vcn_v2_0.c | 874 UVD, 0, mmUVD_LMI_CTRL2), in vcn_v2_0_start_dpg_mode()
1003 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v2_0_start()
1158 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); in vcn_v2_0_stop()
1160 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); in vcn_v2_0_stop()
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| D | vcn_v3_0.c | 972 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
1078 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v3_0_start()
1489 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v3_0_stop()
1491 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v3_0_stop()
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| D | uvd_v6_0.c | 875 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v6_0_stop()
886 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v6_0_stop()
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| D | vcn_v1_0.c | 860 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v1_0_start_spg_mode()
1038 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2, in vcn_v1_0_start_dpg_mode()
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| /drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 48 #define mmUVD_LMI_CTRL2 0x3D3D macro
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| D | uvd_4_2_d.h | 46 #define mmUVD_LMI_CTRL2 0x3d3d macro
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| D | uvd_3_1_d.h | 46 #define mmUVD_LMI_CTRL2 0x3d3d macro
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| D | uvd_5_0_d.h | 52 #define mmUVD_LMI_CTRL2 0x3d3d macro
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| D | uvd_6_0_d.h | 68 #define mmUVD_LMI_CTRL2 0x3d3d macro
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| D | uvd_7_0_offset.h | 150 #define mmUVD_LMI_CTRL2 … macro
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| /drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 328 #define mmUVD_LMI_CTRL2 … macro
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| D | vcn_2_5_offset.h | 955 #define mmUVD_LMI_CTRL2 … macro
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| D | vcn_2_0_0_offset.h | 536 #define mmUVD_LMI_CTRL2 … macro
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| D | vcn_3_0_0_offset.h | 1469 #define mmUVD_LMI_CTRL2 … macro
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