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Searched refs:mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h272 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … macro
Dvcn_2_5_offset.h271 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … macro
Dvcn_2_0_0_offset.h256 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … macro
Dvcn_3_0_0_offset.h499 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH … macro
/drivers/gpu/drm/amd/amdgpu/
Djpeg_v1_0.c237 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()