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Searched refs:mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_d.h42 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f macro
Duvd_6_0_d.h53 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f macro
Duvd_7_0_offset.h108 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_5.c404 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
411 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
457 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
466 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
475 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
1199 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_sriov_start()
1211 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_sriov_start()
Dvcn_v2_0.c338 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
345 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
393 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_mc_resume_dpg_mode()
402 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
411 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_mc_resume_dpg_mode()
1882 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_start_sriov()
1892 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_start_sriov()
Dvcn_v3_0.c425 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
432 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
468 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
477 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
486 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
1275 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_start_sriov()
1286 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_start_sriov()
Duvd_v7_0.c659 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
670 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
804 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
812 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
Dvcn_v1_0.c309 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
316 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
376 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_dpg_mode()
386 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_dpg_mode()
Duvd_v5_0.c257 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v5_0_mc_resume()
Duvd_v6_0.c588 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v6_0_mc_resume()
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h234 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
Dvcn_2_5_offset.h865 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
Dvcn_2_0_0_offset.h944 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
Dvcn_3_0_0_offset.h1283 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro