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Searched refs:mmUVD_MIF_REF_ADDR_CONFIG (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_d.h110 #define mmUVD_MIF_REF_ADDR_CONFIG 0x3993 macro
Duvd_6_0_d.h126 #define mmUVD_MIF_REF_ADDR_CONFIG 0x3993 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h93 #define mmUVD_MIF_REF_ADDR_CONFIG … macro
Dvcn_2_5_offset.h841 #define mmUVD_MIF_REF_ADDR_CONFIG … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c359 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, in vcn_v1_0_mc_resume_spg_mode()
435 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, in vcn_v1_0_mc_resume_dpg_mode()