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Searched refs:mmUVD_MPC_SET_MUXB0_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_offset.h171 #define mmUVD_MPC_SET_MUXB0_BASE_IDX … macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h351 #define mmUVD_MPC_SET_MUXB0_BASE_IDX … macro
Dvcn_2_5_offset.h766 #define mmUVD_MPC_SET_MUXB0_BASE_IDX … macro
Dvcn_2_0_0_offset.h601 #define mmUVD_MPC_SET_MUXB0_BASE_IDX … macro
Dvcn_3_0_0_offset.h1146 #define mmUVD_MPC_SET_MUXB0_BASE_IDX … macro