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Searched refs:mmUVD_RBC_RB_RPTR (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h71 #define mmUVD_RBC_RB_RPTR 0x3DA4 macro
Duvd_4_2_d.h71 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
Duvd_3_1_d.h73 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
Duvd_5_0_d.h77 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
Duvd_6_0_d.h93 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
Duvd_7_0_offset.h198 #define mmUVD_RBC_RB_RPTR … macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c48 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v3_1_ring_get_rptr()
420 WREG32(mmUVD_RBC_RB_RPTR, 0x0); in uvd_v3_1_start()
422 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v3_1_start()
Duvd_v4_2.c62 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v4_2_ring_get_rptr()
356 WREG32(mmUVD_RBC_RB_RPTR, 0x0); in uvd_v4_2_start()
358 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v4_2_start()
Duvd_v5_0.c60 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v5_0_ring_get_rptr()
414 WREG32(mmUVD_RBC_RB_RPTR, 0); in uvd_v5_0_start()
416 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v5_0_start()
Dvcn_v1_0.c932 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); in vcn_v1_0_start_spg_mode()
936 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v1_0_start_spg_mode()
1090 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); in vcn_v1_0_start_dpg_mode()
1094 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v1_0_start_dpg_mode()
1185 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1385 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v1_0_dec_ring_get_rptr()
Dvcn_v2_5.c899 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start_dpg_mode()
903 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start_dpg_mode()
1079 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start()
1081 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start()
1320 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1486 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); in vcn_v2_5_dec_ring_get_rptr()
Dvcn_v2_0.c916 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_0_start_dpg_mode()
920 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_start_dpg_mode()
1076 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_0_start()
1078 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_start()
1120 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1327 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_dec_ring_get_rptr()
Dvcn_v3_0.c1026 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); in vcn_v3_0_start_dpg_mode()
1030 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); in vcn_v3_0_start_dpg_mode()
1192 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); in vcn_v3_0_start()
1194 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); in vcn_v3_0_start()
1449 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1615 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); in vcn_v3_0_dec_ring_get_rptr()
Duvd_v6_0.c81 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v6_0_ring_get_rptr()
836 WREG32(mmUVD_RBC_RB_RPTR, 0); in uvd_v6_0_start()
838 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v6_0_start()
Duvd_v7_0.c75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); in uvd_v7_0_ring_get_rptr()
1083 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); in uvd_v7_0_start()
1085 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); in uvd_v7_0_start()
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h384 #define mmUVD_RBC_RB_RPTR … macro
Dvcn_2_5_offset.h789 #define mmUVD_RBC_RB_RPTR … macro
Dvcn_2_0_0_offset.h680 #define mmUVD_RBC_RB_RPTR … macro
Dvcn_3_0_0_offset.h1173 #define mmUVD_RBC_RB_RPTR … macro