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Searched refs:mmUVD_RBC_RB_WPTR (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h73 #define mmUVD_RBC_RB_WPTR 0x3DA5 macro
Duvd_4_2_d.h72 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
Duvd_3_1_d.h74 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
Duvd_5_0_d.h78 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
Duvd_6_0_d.h94 #define mmUVD_RBC_RB_WPTR 0x3da5 macro
Duvd_7_0_offset.h200 #define mmUVD_RBC_RB_WPTR … macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c62 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v3_1_ring_get_wptr()
76 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v3_1_ring_set_wptr()
423 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v3_1_start()
Duvd_v4_2.c76 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v4_2_ring_get_wptr()
90 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v4_2_ring_set_wptr()
359 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v4_2_start()
Duvd_v5_0.c74 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v5_0_ring_get_wptr()
88 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_ring_set_wptr()
417 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_start()
Dvcn_v1_0.c937 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_start_spg_mode()
1095 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_start_dpg_mode()
1184 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v1_0_stop_dpg_mode()
1260 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_pause_dpg_mode()
1321 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v1_0_pause_dpg_mode()
1399 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); in vcn_v1_0_dec_ring_get_wptr()
1417 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_dec_ring_set_wptr()
Dvcn_v2_0.c921 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_start_dpg_mode()
1079 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_start()
1119 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v2_0_stop_dpg_mode()
1255 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, in vcn_v2_0_pause_dpg_mode()
1344 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); in vcn_v2_0_dec_ring_get_wptr()
1366 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_dec_ring_set_wptr()
Dvcn_v2_5.c904 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start_dpg_mode()
1082 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start()
1319 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v2_5_stop_dpg_mode()
1503 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); in vcn_v2_5_dec_ring_get_wptr()
1521 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_dec_ring_set_wptr()
Dvcn_v3_0.c1031 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v3_0_start_dpg_mode()
1195 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v3_0_start()
1448 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v3_0_stop_dpg_mode()
1632 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); in vcn_v3_0_dec_ring_get_wptr()
1650 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_dec_ring_set_wptr()
Duvd_v6_0.c111 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v6_0_ring_get_wptr()
142 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_ring_set_wptr()
839 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
Duvd_v7_0.c106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); in uvd_v7_0_ring_get_wptr()
140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
1086 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, in uvd_v7_0_start()
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h386 #define mmUVD_RBC_RB_WPTR … macro
Dvcn_2_5_offset.h791 #define mmUVD_RBC_RB_WPTR … macro
Dvcn_2_0_0_offset.h682 #define mmUVD_RBC_RB_WPTR … macro
Dvcn_3_0_0_offset.h1175 #define mmUVD_RBC_RB_WPTR … macro