Searched refs:mmUVD_SCRATCH2 (Results 1 – 8 of 8) sorted by relevance
| /drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 46 #define mmUVD_SCRATCH2 … macro
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| D | vcn_2_5_offset.h | 419 #define mmUVD_SCRATCH2 … macro
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| D | vcn_2_0_0_offset.h | 404 #define mmUVD_SCRATCH2 … macro
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| D | vcn_3_0_0_offset.h | 695 #define mmUVD_SCRATCH2 … macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v1_0.c | 934 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); in vcn_v1_0_start_spg_mode()
1092 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); in vcn_v1_0_start_dpg_mode()
1261 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); in vcn_v1_0_pause_dpg_mode()
1322 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); in vcn_v1_0_pause_dpg_mode()
1414 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, in vcn_v1_0_dec_ring_set_wptr()
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| D | vcn_v2_0.c | 918 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); in vcn_v2_0_start_dpg_mode()
1256 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); in vcn_v2_0_pause_dpg_mode()
1359 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, in vcn_v2_0_dec_ring_set_wptr()
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| D | vcn_v2_5.c | 901 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v2_5_start_dpg_mode()
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| D | vcn_v3_0.c | 1028 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v3_0_start_dpg_mode()
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