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Searched refs:mmUVD_SEMA_CNTL (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h78 #define mmUVD_SEMA_CNTL 0x3D00 macro
Duvd_4_2_d.h38 #define mmUVD_SEMA_CNTL 0x3d00 macro
Duvd_3_1_d.h38 #define mmUVD_SEMA_CNTL 0x3d00 macro
Duvd_5_0_d.h44 #define mmUVD_SEMA_CNTL 0x3d00 macro
Duvd_6_0_d.h55 #define mmUVD_SEMA_CNTL 0x3d00 macro
Duvd_7_0_offset.h122 #define mmUVD_SEMA_CNTL … macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h248 #define mmUVD_SEMA_CNTL … macro
Dvcn_2_5_offset.h815 #define mmUVD_SEMA_CNTL … macro
Dvcn_2_0_0_offset.h476 #define mmUVD_SEMA_CNTL … macro
Dvcn_3_0_0_offset.h1201 #define mmUVD_SEMA_CNTL … macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c674 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v3_1_hw_init()
Duvd_v4_2.c192 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()
Duvd_v5_0.c189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
Duvd_v6_0.c509 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
Duvd_v7_0.c577 mmUVD_SEMA_CNTL), 0)); in uvd_v7_0_hw_init()