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Searched refs:mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h79 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3DB3 macro
Duvd_4_2_d.h80 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 macro
Duvd_3_1_d.h82 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 macro
Duvd_5_0_d.h86 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 macro
Duvd_6_0_d.h102 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 macro
Duvd_7_0_offset.h216 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h402 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … macro
Dvcn_2_5_offset.h817 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … macro
Dvcn_2_0_0_offset.h706 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … macro
Dvcn_3_0_0_offset.h1203 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c666 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v3_1_hw_init()
Duvd_v4_2.c184 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init()
Duvd_v5_0.c181 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v5_0_hw_init()
Duvd_v6_0.c501 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init()
Duvd_v7_0.c567 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0); in uvd_v7_0_hw_init()