Searched refs:mmUVD_UDEC_DBW_ADDR_CONFIG (Results 1 – 14 of 14) sorted by relevance
| /drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 87 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3BD5 macro
|
| D | uvd_4_2_d.h | 36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 macro
|
| D | uvd_3_1_d.h | 36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 macro
|
| D | uvd_5_0_d.h | 36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 macro
|
| D | uvd_6_0_d.h | 36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 macro
|
| D | uvd_7_0_offset.h | 64 #define mmUVD_UDEC_DBW_ADDR_CONFIG … macro
|
| /drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 152 #define mmUVD_UDEC_DBW_ADDR_CONFIG … macro
|
| /drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v3_1.c | 268 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
|
| D | uvd_v4_2.c | 571 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
|
| D | uvd_v5_0.c | 280 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
|
| D | vcn_v1_0.c | 347 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, in vcn_v1_0_mc_resume_spg_mode()
423 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, in vcn_v1_0_mc_resume_dpg_mode()
|
| D | uvd_v6_0.c | 611 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v6_0_mc_resume()
|
| D | uvd_v7_0.c | 700 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG, in uvd_v7_0_mc_resume()
|
| D | gfx_v6_0.c | 1723 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in gfx_v6_0_constants_init()
|