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Searched refs:mmUVD_VCPU_CACHE_OFFSET0 (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h88 #define mmUVD_VCPU_CACHE_OFFSET0 0x3D36 macro
Duvd_4_2_d.h60 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
Duvd_3_1_d.h62 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
Duvd_5_0_d.h66 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
Duvd_6_0_d.h82 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
Duvd_7_0_offset.h178 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_5.c408 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
416 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_5_mc_resume()
463 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
470 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
482 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_mc_resume_dpg_mode()
1207 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); in vcn_v2_5_sriov_start()
1219 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_sriov_start()
Dvcn_v3_0.c429 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v3_0_mc_resume()
437 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v3_0_mc_resume()
474 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
481 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
493 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_mc_resume_dpg_mode()
1282 mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_start_sriov()
1293 mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_start_sriov()
Dvcn_v2_0.c342 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_0_mc_resume()
350 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_0_mc_resume()
399 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
406 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
418 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_0_mc_resume_dpg_mode()
1902 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_0_start_sriov()
Duvd_v7_0.c667 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in uvd_v7_0_mc_resume()
675 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, in uvd_v7_0_mc_resume()
809 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); in uvd_v7_0_sriov_start()
817 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in uvd_v7_0_sriov_start()
Dvcn_v1_0.c313 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v1_0_mc_resume_spg_mode()
321 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v1_0_mc_resume_spg_mode()
382 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, in vcn_v1_0_mc_resume_dpg_mode()
391 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v1_0_mc_resume_dpg_mode()
Duvd_v3_1.c244 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); in uvd_v3_1_mc_resume()
Duvd_v4_2.c547 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); in uvd_v4_2_mc_resume()
Duvd_v5_0.c264 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v5_0_mc_resume()
Duvd_v6_0.c595 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v6_0_mc_resume()
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h364 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
Dvcn_2_5_offset.h685 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
Dvcn_2_0_0_offset.h614 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
Dvcn_3_0_0_offset.h1061 #define mmUVD_VCPU_CACHE_OFFSET0 … macro