Home
last modified time | relevance | path

Searched refs:mmUVD_VCPU_CACHE_SIZE1_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_offset.h185 #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX … macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h371 #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX … macro
Dvcn_2_5_offset.h692 #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX … macro
Dvcn_2_0_0_offset.h621 #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX … macro
Dvcn_3_0_0_offset.h1068 #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX … macro