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Searched refs:mmUVD_VCPU_CACHE_SIZE5_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_offset.h708 #define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX … macro
Dvcn_2_0_0_offset.h637 #define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX … macro
Dvcn_3_0_0_offset.h1084 #define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX … macro