Searched refs:mmVCE_RB_WPTR (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/amd/include/asic_reg/vce/ |
| D | vce_1_0_d.h | 46 #define mmVCE_RB_WPTR 0x8064 macro
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| D | vce_2_0_d.h | 45 #define mmVCE_RB_WPTR 0x8064 macro
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| D | vce_3_0_d.h | 45 #define mmVCE_RB_WPTR 0x8064 macro
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| D | vce_4_0_offset.h | 88 #define mmVCE_RB_WPTR … macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | vce_v2_0.c | 77 return RREG32(mmVCE_RB_WPTR); in vce_v2_0_ring_get_wptr()
94 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v2_0_ring_set_wptr()
245 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v2_0_start()
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| D | vce_v3_0.c | 122 v = RREG32(mmVCE_RB_WPTR); in vce_v3_0_ring_get_wptr()
153 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
282 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_start()
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| D | vce_v4_0.c | 88 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); in vce_v4_0_ring_get_wptr()
114 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), in vce_v4_0_ring_set_wptr()
343 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
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