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Searched refs:mmVCE_RB_WPTR2 (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/vce/
Dvce_1_0_d.h47 #define mmVCE_RB_WPTR2 0x805F macro
Dvce_2_0_d.h40 #define mmVCE_RB_WPTR2 0x805f macro
Dvce_3_0_d.h40 #define mmVCE_RB_WPTR2 0x805f macro
Dvce_4_0_offset.h78 #define mmVCE_RB_WPTR2 … macro
/drivers/gpu/drm/amd/amdgpu/
Dvce_v2_0.c79 return RREG32(mmVCE_RB_WPTR2); in vce_v2_0_ring_get_wptr()
96 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v2_0_ring_set_wptr()
252 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v2_0_start()
Dvce_v3_0.c124 v = RREG32(mmVCE_RB_WPTR2); in vce_v3_0_ring_get_wptr()
155 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
289 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_start()
Dvce_v4_0.c90 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); in vce_v4_0_ring_get_wptr()
117 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), in vce_v4_0_ring_set_wptr()
351 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr)); in vce_v4_0_start()