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Searched refs:mmVCE_STATUS (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvce_v4_0.c131 RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS)); in vce_v4_0_firmware_loaded()
304 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), in vce_v4_0_sriov_start()
311 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), in vce_v4_0_sriov_start()
316 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), in vce_v4_0_sriov_start()
365 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK, in vce_v4_0_start()
377 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK); in vce_v4_0_start()
399 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0); in vce_v4_0_stop()
713 if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
718 if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
Dvce_v2_0.c122 uint32_t status = RREG32(mmVCE_STATUS); in vce_v2_0_firmware_loaded()
236 WREG32_P(mmVCE_STATUS, 1, ~1); in vce_v2_0_start()
265 WREG32_P(mmVCE_STATUS, 0, ~1); in vce_v2_0_start()
305 WREG32(mmVCE_STATUS, 0); in vce_v2_0_stop()
Dvce_v3_0.c241 uint32_t status = RREG32(mmVCE_STATUS); in vce_v3_0_firmware_loaded()
351 WREG32(mmVCE_STATUS, 0); in vce_v3_0_stop()
625 if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { in vce_v3_0_check_soft_reset()
630 if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { in vce_v3_0_check_soft_reset()
/drivers/gpu/drm/amd/include/asic_reg/vce/
Dvce_1_0_d.h49 #define mmVCE_STATUS 0x8001 macro
Dvce_2_0_d.h27 #define mmVCE_STATUS 0x8001 macro
Dvce_3_0_d.h27 #define mmVCE_STATUS 0x8001 macro
Dvce_4_0_offset.h28 #define mmVCE_STATUS … macro