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Searched refs:mmVCE_UENC_REG_CLOCK_GATING (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvce_v2_0.c174 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_mc_resume()
323 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
325 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
339 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
341 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
371 orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
374 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
377 WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00); in vce_v2_0_set_dyn_cg()
Dvce_v3_0.c197 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
199 WREG32(mmVCE_UENC_REG_CLOCK_GATING, data); in vce_v3_0_set_vce_sw_clock_gating()
221 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
223 WREG32(mmVCE_UENC_REG_CLOCK_GATING, data); in vce_v3_0_set_vce_sw_clock_gating()
531 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v3_0_mc_resume()
Dvce_v4_0.c606 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F); in vce_v4_0_mc_resume()
833 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));
835 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);
857 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));
859 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);
/drivers/gpu/drm/amd/include/asic_reg/vce/
Dvce_1_0_d.h55 #define mmVCE_UENC_REG_CLOCK_GATING 0x8170 macro
Dvce_2_0_d.h52 #define mmVCE_UENC_REG_CLOCK_GATING 0x81f0 macro
Dvce_3_0_d.h56 #define mmVCE_UENC_REG_CLOCK_GATING 0x81f0 macro
Dvce_4_0_offset.h118 #define mmVCE_UENC_REG_CLOCK_GATING … macro