Searched refs:mmVM_L2_CNTL2 (Results 1 – 16 of 16) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 156 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); in gfxhub_v1_0_init_cache_regs()
159 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); in gfxhub_v1_0_init_cache_regs()
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| D | gmc_v6_0.c | 500 WREG32(mmVM_L2_CNTL2, in gmc_v6_0_gart_enable()
606 WREG32(mmVM_L2_CNTL2, 0); in gmc_v6_0_gart_disable()
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| D | mmhub_v1_0.c | 176 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); in mmhub_v1_0_init_cache_regs()
179 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); in mmhub_v1_0_init_cache_regs()
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| D | gmc_v8_0.c | 875 tmp = RREG32(mmVM_L2_CNTL2); in gmc_v8_0_gart_enable()
878 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v8_0_gart_enable()
1005 WREG32(mmVM_L2_CNTL2, 0); in gmc_v8_0_gart_disable()
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| D | gmc_v7_0.c | 644 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v7_0_gart_enable()
755 WREG32(mmVM_L2_CNTL2, 0); in gmc_v7_0_gart_disable()
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| /drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_7_0_d.h | 542 #define mmVM_L2_CNTL2 0x501 macro
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| D | gmc_8_2_d.h | 600 #define mmVM_L2_CNTL2 0x501 macro
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| D | gmc_6_0_d.h | 1258 #define mmVM_L2_CNTL2 0x0501 macro
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| D | gmc_7_1_d.h | 575 #define mmVM_L2_CNTL2 0x501 macro
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| D | gmc_8_1_d.h | 598 #define mmVM_L2_CNTL2 0x501 macro
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| /drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
| D | mmhub_9_3_0_offset.h | 1282 #define mmVM_L2_CNTL2 … macro
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| D | mmhub_1_0_offset.h | 1266 #define mmVM_L2_CNTL2 … macro
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| D | mmhub_9_1_offset.h | 1298 #define mmVM_L2_CNTL2 … macro
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| /drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 1167 #define mmVM_L2_CNTL2 … macro
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| D | gc_9_1_offset.h | 1193 #define mmVM_L2_CNTL2 … macro
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| D | gc_9_2_1_offset.h | 1131 #define mmVM_L2_CNTL2 … macro
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