Searched refs:mpll_cfg (Results 1 – 8 of 8) sorted by relevance
227 const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; in dw_hdmi_rockchip_mode_valid() local232 for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { in dw_hdmi_rockchip_mode_valid()233 if (pclk == mpll_cfg[i].mpixelclock) { in dw_hdmi_rockchip_mode_valid()408 .mpll_cfg = rockchip_mpll_cfg,425 .mpll_cfg = rockchip_mpll_cfg,445 .mpll_cfg = rockchip_mpll_cfg,463 .mpll_cfg = rockchip_mpll_cfg,
54 static struct mpll_cfg dcn21_mpll_cfg_ref[] = {186 cfg->mpll_cfg = dcn21_mpll_cfg_ref[0]; in update_cfg_data()189 cfg->mpll_cfg = dcn21_mpll_cfg_ref[1]; in update_cfg_data()192 cfg->mpll_cfg = dcn21_mpll_cfg_ref[2]; in update_cfg_data()195 cfg->mpll_cfg = dcn21_mpll_cfg_ref[3]; in update_cfg_data()
59 static struct mpll_cfg dcn2_mpll_cfg[] = {226 cfg->mpll_cfg = dcn2_mpll_cfg[0]; in update_cfg_data()229 cfg->mpll_cfg = dcn2_mpll_cfg[1]; in update_cfg_data()232 cfg->mpll_cfg = dcn2_mpll_cfg[2]; in update_cfg_data()235 cfg->mpll_cfg = dcn2_mpll_cfg[3]; in update_cfg_data()
246 struct mpll_cfg { struct292 struct mpll_cfg mpll_cfg; argument
171 .mpll_cfg = imx_mpll_cfg,178 .mpll_cfg = imx_mpll_cfg,
575 plat_data->mpll_cfg = variant->mpll_cfg; in sun8i_hdmi_phy_set_ops()623 .mpll_cfg = sun50i_h6_mpll_cfg,
156 const struct dw_hdmi_mpll_config *mpll_cfg; member
1454 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; in hdmi_phy_configure_dwc_hdmi_3d_tx()