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Searched refs:mux_clks (Results 1 – 8 of 8) sorted by relevance

/drivers/clk/samsung/
Dclk-exynos7.c189 .mux_clks = topc_mux_clks,
381 .mux_clks = top0_mux_clks,
563 .mux_clks = top1_mux_clks,
612 .mux_clks = ccore_mux_clks,
679 .mux_clks = peric0_mux_clks,
803 .mux_clks = peric1_mux_clks,
858 .mux_clks = peris_mux_clks,
968 .mux_clks = fsys0_mux_clks,
1097 .mux_clks = fsys1_mux_clks,
1210 .mux_clks = mscl_mux_clks,
[all …]
Dclk-exynos5260.c132 .mux_clks = aud_mux_clks,
322 .mux_clks = disp_mux_clks,
388 .mux_clks = egl_mux_clks,
488 .mux_clks = fsys_mux_clks,
577 .mux_clks = g2d_mux_clks,
640 .mux_clks = g3d_mux_clks,
773 .mux_clks = gscl_mux_clks,
892 .mux_clks = isp_mux_clks,
958 .mux_clks = kfc_mux_clks,
1012 .mux_clks = mfc_mux_clks,
[all …]
Dclk-exynos3250.c237 static const struct samsung_mux_clock mux_clks[] __initconst = { variable
775 .mux_clks = mux_clks,
776 .nr_mux_clks = ARRAY_SIZE(mux_clks),
922 .mux_clks = dmc_mux_clks,
Dclk-exynos5433.c791 .mux_clks = top_mux_clks,
874 .mux_clks = cpif_mux_clks,
1526 .mux_clks = mif_mux_clks,
2333 .mux_clks = fsys_mux_clks,
2456 .mux_clks = g2d_mux_clks,
2880 .mux_clks = disp_mux_clks,
3052 .mux_clks = aud_mux_clks,
3208 .mux_clks = bus2_mux_clks,
3337 .mux_clks = g3d_mux_clks,
3482 .mux_clks = gscl_mux_clks,
[all …]
Dclk.c363 if (cmu->mux_clks) in samsung_cmu_register_one()
364 samsung_clk_register_mux(ctx, cmu->mux_clks, in samsung_cmu_register_one()
Dclk-s5pv210.c374 static const struct samsung_mux_clock mux_clks[] __initconst = { variable
774 samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks)); in __s5pv210_clk_init()
Dclk-exynos5410.c257 .mux_clks = exynos5410_mux_clks,
Dclk.h288 const struct samsung_mux_clock *mux_clks; member