| /drivers/gpu/drm/omapdrm/ |
| D | omap_drv.c | 135 for (i = 0; i < priv->num_pipes; i++) { in omap_disconnect_pipelines()
146 priv->num_pipes = 0; in omap_disconnect_pipelines()
166 pipe = &priv->pipes[priv->num_pipes++]; in omap_connect_pipelines()
169 if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) { in omap_connect_pipelines()
258 if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) { in omap_modeset_init()
265 plane_crtc_mask = (1 << priv->num_pipes) - 1; in omap_modeset_init()
268 enum drm_plane_type type = i < priv->num_pipes in omap_modeset_init()
287 for (i = 0; i < priv->num_pipes; i++) { in omap_modeset_init()
312 sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]), in omap_modeset_init()
319 for (i = 0; i < priv->num_pipes; ++i) { in omap_modeset_init()
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| D | omap_drv.h | 52 unsigned int num_pipes; member
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| /drivers/gpu/drm/tidss/ |
| D | tidss_kms.c | 124 u32 num_pipes = 0; in tidss_dispc_modeset_init() local
181 pipes[num_pipes].hw_videoport = i; in tidss_dispc_modeset_init()
182 pipes[num_pipes].bridge = bridge; in tidss_dispc_modeset_init()
183 pipes[num_pipes].enc_type = enc_type; in tidss_dispc_modeset_init()
184 num_pipes++; in tidss_dispc_modeset_init()
188 crtc_mask = (1 << num_pipes) - 1; in tidss_dispc_modeset_init()
192 for (i = 0; i < num_pipes; ++i) { in tidss_dispc_modeset_init()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 983 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
1141 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml_rq_dlg_get_dlg_params()
1142 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1217 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1263 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1264 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1280 for (k = 0; k < num_pipes; ++k) { in dml_rq_dlg_get_dlg_params()
1285 for (i = 0; i < num_pipes; i++) { in dml_rq_dlg_get_dlg_params()
1291 for (j = i; j < num_pipes; j++) { in dml_rq_dlg_get_dlg_params()
1338 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
[all …]
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| D | display_rq_dlg_calc_30.h | 61 const unsigned int num_pipes,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 832 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
985 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml_rq_dlg_get_dlg_params()
986 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1068 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1117 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1118 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1146 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1152 num_pipes, in dml_rq_dlg_get_dlg_params()
1157 num_pipes, in dml_rq_dlg_get_dlg_params()
1159 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_21.h | 65 const unsigned int num_pipes,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20.c | 48 const unsigned int num_pipes,
786 const unsigned int num_pipes, in dml20_rq_dlg_get_dlg_params() argument
939 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1028 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1074 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1075 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1098 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1103 num_pipes, in dml20_rq_dlg_get_dlg_params()
1107 num_pipes, in dml20_rq_dlg_get_dlg_params()
[all …]
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| D | display_rq_dlg_calc_20v2.c | 48 const unsigned int num_pipes,
786 const unsigned int num_pipes, in dml20v2_rq_dlg_get_dlg_params() argument
939 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20v2_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1029 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1075 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1076 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1099 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1104 num_pipes, in dml20v2_rq_dlg_get_dlg_params()
1108 num_pipes, in dml20v2_rq_dlg_get_dlg_params()
[all …]
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| D | display_rq_dlg_calc_20.h | 65 const unsigned int num_pipes,
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| D | display_rq_dlg_calc_20v2.h | 65 const unsigned int num_pipes,
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_vba.c | 47 unsigned int num_pipes);
54 unsigned int num_pipes) in dml_get_voltage_level() argument
58 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
60 sizeof(display_e2e_pipe_params_st) * num_pipes) != 0; in dml_get_voltage_level()
64 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
65 mode_lib->vba.cache_num_pipes = num_pipes; in dml_get_voltage_level()
80 …ruct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes) \
82 recalculate_params(mode_lib, pipes, num_pipes); \
108 …de_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int wh…
111 recalculate_params(mode_lib, pipes, num_pipes); \
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| D | display_mode_vba.h | 34 …struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
58 …de_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int wh…
109 unsigned int num_pipes);
113 unsigned int num_pipes);
117 unsigned int num_pipes);
121 unsigned int num_pipes);
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| D | display_mode_lib.h | 53 const unsigned int num_pipes,
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| /drivers/gpu/drm/radeon/ |
| D | r420.c | 94 unsigned num_pipes; in r420_pipes_init() local
105 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; in r420_pipes_init()
110 num_pipes = 1; in r420_pipes_init()
112 rdev->num_gb_pipes = num_pipes; in r420_pipes_init()
114 switch (num_pipes) { in r420_pipes_init()
117 num_pipes = 1; in r420_pipes_init()
132 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); in r420_pipes_init()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.h | 143 int num_pipes, unsigned int vmin, unsigned int vmax,
146 int num_pipes,
149 int num_pipes, const struct dc_static_screen_params *params);
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| D | dcn10_dwb.c | 52 caps->num_pipes = 2; in dwb1_get_caps()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer.h | 96 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
111 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
115 int num_pipes,
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 1717 uint8_t i, num_pipes; in dce110_set_displaymarks() local
1720 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { in dce110_set_displaymarks()
1731 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], in dce110_set_displaymarks()
1732 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], in dce110_set_displaymarks()
1733 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], in dce110_set_displaymarks()
1734 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], in dce110_set_displaymarks()
1737 num_pipes++; in dce110_set_displaymarks()
1740 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], in dce110_set_displaymarks()
1741 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], in dce110_set_displaymarks()
1742 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], in dce110_set_displaymarks()
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| /drivers/staging/media/atomisp/pci/ |
| D | sh_css.c | 134 int num_pipes; member
1494 for (i = 0; i < stream->num_pipes; i++) { in sh_css_invalidate_shading_tables()
1907 for (i = 1; i < stream->num_pipes; i++) in map_sp_threads()
2013 for (i = 1; i < stream->num_pipes && 0 == err; i++) { in create_host_pipeline_structure()
2163 for (i = 1; i < stream->num_pipes && 0 == err; i++) { in create_host_pipeline()
4677 n = event->pipe->stream->num_pipes; in ia_css_dequeue_psys_event()
4817 for (i = 1; i < stream->num_pipes && 0 == err ; i++) { in sh_css_pipe_start()
4884 for (i = 1; i < stream->num_pipes; i++) { in sh_css_pipe_start()
5061 for (i = 0; i < stream->num_pipes; i++) in sh_css_pipes_stop()
5165 for (i = 0; i < stream->num_pipes; i++) { in sh_css_pipes_have_stopped()
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| D | ia_css_stream.h | 38 int num_pipes; member
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| D | ia_css_stream_public.h | 181 int num_pipes,
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| /drivers/gpu/drm/mediatek/ |
| D | mtk_drm_drv.h | 38 unsigned int num_pipes; member
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dwb.h | 150 unsigned int num_pipes; /* number of DWB pipes */ member
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| /drivers/staging/media/atomisp/pci/runtime/debug/interface/ |
| D | ia_css_debug.h | 400 int num_pipes);
|