/drivers/crypto/cavium/nitrox/ |
D | nitrox_hal.c | 43 u64 offset; in nitrox_config_emu_unit() local 57 offset = EMU_WD_INT_ENA_W1SX(i); in nitrox_config_emu_unit() 58 nitrox_write_csr(ndev, offset, emu_wd_int.value); in nitrox_config_emu_unit() 59 offset = EMU_GE_INT_ENA_W1SX(i); in nitrox_config_emu_unit() 60 nitrox_write_csr(ndev, offset, emu_ge_int.value); in nitrox_config_emu_unit() 69 u64 offset; in reset_pkt_input_ring() local 72 offset = NPS_PKT_IN_INSTR_CTLX(ring); in reset_pkt_input_ring() 73 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring() 75 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in reset_pkt_input_ring() 80 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring() [all …]
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/drivers/gpio/ |
D | gpio-eic-sprd.c | 140 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset, in sprd_eic_update() argument 145 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_update() 153 tmp |= BIT(SPRD_EIC_BIT(offset)); in sprd_eic_update() 155 tmp &= ~BIT(SPRD_EIC_BIT(offset)); in sprd_eic_update() 161 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg) in sprd_eic_read() argument 165 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_read() 167 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); in sprd_eic_read() 170 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset) in sprd_eic_request() argument 172 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1); in sprd_eic_request() 176 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset) in sprd_eic_free() argument [all …]
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D | gpio-cs5535.c | 83 static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset, in __cs5535_gpio_set() argument 86 if (offset < 16) in __cs5535_gpio_set() 88 outl(1 << offset, chip->base + reg); in __cs5535_gpio_set() 91 errata_outl(chip, 1 << (offset - 16), reg); in __cs5535_gpio_set() 94 void cs5535_gpio_set(unsigned offset, unsigned int reg) in cs5535_gpio_set() argument 100 __cs5535_gpio_set(chip, offset, reg); in cs5535_gpio_set() 105 static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset, in __cs5535_gpio_clear() argument 108 if (offset < 16) in __cs5535_gpio_clear() 110 outl(1 << (offset + 16), chip->base + reg); in __cs5535_gpio_clear() 113 errata_outl(chip, 1 << offset, reg); in __cs5535_gpio_clear() [all …]
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D | gpio-aspeed.c | 251 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) in to_bank() argument 253 unsigned int bank = GPIO_BANK(offset); in to_bank() 265 struct aspeed_gpio *gpio, unsigned int offset) in find_bank_props() argument 270 if (props->bank == GPIO_BANK(offset)) in find_bank_props() 278 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) in have_gpio() argument 280 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_gpio() 281 const struct aspeed_gpio_bank *bank = to_bank(offset); in have_gpio() 282 unsigned int group = GPIO_OFFSET(offset) / 8; in have_gpio() 285 (!props || ((props->input | props->output) & GPIO_BIT(offset))); in have_gpio() 288 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) in have_input() argument [all …]
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D | gpio-sprd.c | 48 static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset, in sprd_gpio_update() argument 53 offset / SPRD_GPIO_BANK_NR); in sprd_gpio_update() 61 tmp |= BIT(SPRD_GPIO_BIT(offset)); in sprd_gpio_update() 63 tmp &= ~BIT(SPRD_GPIO_BIT(offset)); in sprd_gpio_update() 69 static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, u16 reg) in sprd_gpio_read() argument 73 offset / SPRD_GPIO_BANK_NR); in sprd_gpio_read() 75 return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset))); in sprd_gpio_read() 78 static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset) in sprd_gpio_request() argument 80 sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 1); in sprd_gpio_request() 84 static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset) in sprd_gpio_free() argument [all …]
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/drivers/net/wireless/ath/ath10k/ |
D | qmi_wlfw_v01.c | 17 .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01, 26 .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01, 35 .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01, 44 .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01, 53 .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01, 66 .offset = offsetof(struct wlfw_ce_svc_pipe_cfg_s_v01, 75 .offset = offsetof(struct wlfw_ce_svc_pipe_cfg_s_v01, 84 .offset = offsetof(struct wlfw_ce_svc_pipe_cfg_s_v01, 97 .offset = offsetof(struct wlfw_shadow_reg_cfg_s_v01, 106 .offset = offsetof(struct wlfw_shadow_reg_cfg_s_v01, [all …]
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/drivers/pinctrl/ |
D | pinctrl-coh901.c | 211 static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) in u300_gpio_get() argument 215 return !!(readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset)); in u300_gpio_get() 218 static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in u300_gpio_set() argument 226 val = readl(U300_PIN_REG(offset, dor)); in u300_gpio_set() 228 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); in u300_gpio_set() 230 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); in u300_gpio_set() 235 static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in u300_gpio_direction_input() argument 242 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_direction_input() 244 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); in u300_gpio_direction_input() 245 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_direction_input() [all …]
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D | pinctrl-da9062.c | 30 #define DA9062_TYPE(offset) (4 * (offset % 2)) argument 31 #define DA9062_PIN_SHIFT(offset) (4 * (offset % 2)) argument 45 unsigned int offset) in da9062_pctl_get_pin_mode() argument 50 ret = regmap_read(regmap, DA9062AA_GPIO_0_1 + (offset >> 1), &val); in da9062_pctl_get_pin_mode() 54 val >>= DA9062_PIN_SHIFT(offset); in da9062_pctl_get_pin_mode() 61 unsigned int offset, unsigned int mode_req) in da9062_pctl_set_pin_mode() argument 69 mode <<= DA9062_PIN_SHIFT(offset); in da9062_pctl_set_pin_mode() 70 mask = DA9062AA_GPIO0_PIN_MASK << DA9062_PIN_SHIFT(offset); in da9062_pctl_set_pin_mode() 72 ret = regmap_update_bits(regmap, DA9062AA_GPIO_0_1 + (offset >> 1), in da9062_pctl_set_pin_mode() 75 pctl->pin_config[offset] = mode_req; in da9062_pctl_set_pin_mode() [all …]
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/drivers/thunderbolt/ |
D | cap.c | 21 u32 value, offset; in tb_port_enable_tmu() local 29 offset = 0x26; in tb_port_enable_tmu() 31 offset = 0x2a; in tb_port_enable_tmu() 35 ret = tb_sw_read(sw, &value, TB_CFG_SWITCH, offset, 1); in tb_port_enable_tmu() 44 return tb_sw_write(sw, &value, TB_CFG_SWITCH, offset, 1); in tb_port_enable_tmu() 72 int tb_port_next_cap(struct tb_port *port, unsigned int offset) in tb_port_next_cap() argument 77 if (!offset) in tb_port_next_cap() 80 ret = tb_port_read(port, &header, TB_CFG_PORT, offset, 1); in tb_port_next_cap() 89 int offset = 0; in __tb_port_find_cap() local 95 offset = tb_port_next_cap(port, offset); in __tb_port_find_cap() [all …]
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/drivers/misc/ocxl/ |
D | mmio.c | 7 int ocxl_global_mmio_read32(struct ocxl_afu *afu, size_t offset, in ocxl_global_mmio_read32() argument 10 if (offset > afu->config.global_mmio_size - 4) in ocxl_global_mmio_read32() 20 *val = readl_be((char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_read32() 24 *val = readl((char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_read32() 32 int ocxl_global_mmio_read64(struct ocxl_afu *afu, size_t offset, in ocxl_global_mmio_read64() argument 35 if (offset > afu->config.global_mmio_size - 8) in ocxl_global_mmio_read64() 45 *val = readq_be((char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_read64() 49 *val = readq((char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_read64() 57 int ocxl_global_mmio_write32(struct ocxl_afu *afu, size_t offset, in ocxl_global_mmio_write32() argument 60 if (offset > afu->config.global_mmio_size - 4) in ocxl_global_mmio_write32() [all …]
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/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
D | init.c | 43 init->offset, init_exec(init) ? \ 365 return bit_I.offset; in init_table() 377 init_table_(struct nvbios_init *init, u16 offset, const char *name) in init_table_() argument 382 if (len >= offset + 2) { in init_table_() 383 data = nvbios_rd16(bios, data + offset); in init_table_() 461 init_xlat_(struct nvbios_init *init, u8 index, u8 offset) in init_xlat_() argument 468 return nvbios_rd08(bios, data + offset); in init_xlat_() 586 u8 opcode = nvbios_rd08(bios, init->offset); in init_reserved() 600 cont(" 0x%02x", nvbios_rd08(bios, init->offset + i)); in init_reserved() 602 init->offset += length; in init_reserved() [all …]
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/drivers/staging/media/atomisp/pci/css_2400_system/hive/ |
D | ia_css_isp_configs.c | 35 unsigned int offset = 0; in ia_css_configure_iterator() local 40 offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset; in ia_css_configure_iterator() 44 &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], in ia_css_configure_iterator() 63 unsigned int offset = 0; in ia_css_configure_copy_output() local 68 offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset; in ia_css_configure_copy_output() 72 &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], in ia_css_configure_copy_output() 91 unsigned int offset = 0; in ia_css_configure_crop() local 96 offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset; in ia_css_configure_crop() 100 &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], in ia_css_configure_crop() 119 unsigned int offset = 0; in ia_css_configure_fpn() local [all …]
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/drivers/staging/media/atomisp/pci/css_2401_system/hive/ |
D | ia_css_isp_configs.c | 35 unsigned int offset = 0; in ia_css_configure_iterator() local 40 offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset; in ia_css_configure_iterator() 44 &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], in ia_css_configure_iterator() 63 unsigned int offset = 0; in ia_css_configure_copy_output() local 68 offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset; in ia_css_configure_copy_output() 72 &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], in ia_css_configure_copy_output() 91 unsigned int offset = 0; in ia_css_configure_crop() local 96 offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset; in ia_css_configure_crop() 100 &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], in ia_css_configure_crop() 119 unsigned int offset = 0; in ia_css_configure_fpn() local [all …]
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/drivers/gpu/drm/i915/display/ |
D | dvo_ns2501.c | 195 u8 offset; member 301 [0] = { .offset = 0x0a, .value = 0x81, }, 303 [1] = { .offset = 0x12, .value = 0x02, }, 304 [2] = { .offset = 0x18, .value = 0x07, }, 305 [3] = { .offset = 0x19, .value = 0x00, }, 306 [4] = { .offset = 0x1a, .value = 0x00, }, /* PLL?, ignored */ 308 [5] = { .offset = 0x1e, .value = 0x02, }, 309 [6] = { .offset = 0x1f, .value = 0x40, }, 310 [7] = { .offset = 0x20, .value = 0x00, }, 311 [8] = { .offset = 0x21, .value = 0x00, }, [all …]
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/drivers/net/ipa/ |
D | ipa_qmi_msg.c | 20 .offset = offsetof(struct ipa_indication_register_req, 30 .offset = offsetof(struct ipa_indication_register_req, 40 .offset = offsetof(struct ipa_indication_register_req, 50 .offset = offsetof(struct ipa_indication_register_req, 60 .offset = offsetof(struct ipa_indication_register_req, 70 .offset = offsetof(struct ipa_indication_register_req, 87 .offset = offsetof(struct ipa_indication_register_rsp, 105 .offset = offsetof(struct ipa_driver_init_complete_req, 122 .offset = offsetof(struct ipa_driver_init_complete_rsp, 140 .offset = offsetof(struct ipa_init_complete_ind, [all …]
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/drivers/net/wireless/ath/ath6kl/ |
D | bmi.c | 118 u32 offset; in ath6kl_bmi_read() local 143 offset = 0; in ath6kl_bmi_read() 144 memcpy(&(ar->bmi.cmd_buf[offset]), &cid, sizeof(cid)); in ath6kl_bmi_read() 145 offset += sizeof(cid); in ath6kl_bmi_read() 146 memcpy(&(ar->bmi.cmd_buf[offset]), &addr, sizeof(addr)); in ath6kl_bmi_read() 147 offset += sizeof(addr); in ath6kl_bmi_read() 148 memcpy(&(ar->bmi.cmd_buf[offset]), &rx_len, sizeof(rx_len)); in ath6kl_bmi_read() 149 offset += sizeof(len); in ath6kl_bmi_read() 151 ret = ath6kl_hif_bmi_write(ar, ar->bmi.cmd_buf, offset); in ath6kl_bmi_read() 174 u32 offset; in ath6kl_bmi_write() local [all …]
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/drivers/gpu/drm/tegra/ |
D | trace.h | 11 TP_PROTO(struct device *dev, unsigned int offset, u32 value), 12 TP_ARGS(dev, offset, value), 15 __field(unsigned int, offset) 20 __entry->offset = offset; 23 TP_printk("%s %04x %08x", dev_name(__entry->dev), __entry->offset, 28 TP_PROTO(struct device *dev, unsigned int offset, u32 value), 29 TP_ARGS(dev, offset, value)); 31 TP_PROTO(struct device *dev, unsigned int offset, u32 value), 32 TP_ARGS(dev, offset, value)); 35 TP_PROTO(struct device *dev, unsigned int offset, u32 value), [all …]
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/drivers/net/ethernet/qlogic/qed/ |
D | qed_debug.c | 1048 u32 offset = 0; in qed_dump_str_param() local 1051 offset += qed_dump_str(char_buf + offset, dump, param_name); in qed_dump_str_param() 1055 *(char_buf + offset) = 1; in qed_dump_str_param() 1056 offset++; in qed_dump_str_param() 1059 offset += qed_dump_str(char_buf + offset, dump, param_val); in qed_dump_str_param() 1062 offset += qed_dump_align(char_buf + offset, dump, offset); in qed_dump_str_param() 1064 return BYTES_TO_DWORDS(offset); in qed_dump_str_param() 1074 u32 offset = 0; in qed_dump_num_param() local 1077 offset += qed_dump_str(char_buf + offset, dump, param_name); in qed_dump_num_param() 1081 *(char_buf + offset) = 0; in qed_dump_num_param() [all …]
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/drivers/pinctrl/spear/ |
D | pinctrl-plgpio.c | 71 int (*o2p)(int offset); /* offset_to_pin */ 82 u32 offset = PIN_OFFSET(pin); in is_plgpio_set() local 86 return !!(val & (1 << offset)); in is_plgpio_set() 91 u32 offset = PIN_OFFSET(pin); in plgpio_reg_set() local 95 writel_relaxed(val | (1 << offset), reg_off); in plgpio_reg_set() 100 u32 offset = PIN_OFFSET(pin); in plgpio_reg_reset() local 104 writel_relaxed(val & ~(1 << offset), reg_off); in plgpio_reg_reset() 108 static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset) in plgpio_direction_input() argument 115 offset = plgpio->p2o(offset); in plgpio_direction_input() 116 if (offset == -1) in plgpio_direction_input() [all …]
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/drivers/infiniband/sw/rxe/ |
D | rxe_hdr.h | 25 u8 offset; /* bth offset from pkt->hdr */ member 283 return __bth_opcode(pkt->hdr + pkt->offset); in bth_opcode() 288 __bth_set_opcode(pkt->hdr + pkt->offset, opcode); in bth_set_opcode() 293 return __bth_se(pkt->hdr + pkt->offset); in bth_se() 298 __bth_set_se(pkt->hdr + pkt->offset, se); in bth_set_se() 303 return __bth_mig(pkt->hdr + pkt->offset); in bth_mig() 308 __bth_set_mig(pkt->hdr + pkt->offset, mig); in bth_set_mig() 313 return __bth_pad(pkt->hdr + pkt->offset); in bth_pad() 318 __bth_set_pad(pkt->hdr + pkt->offset, pad); in bth_set_pad() 323 return __bth_tver(pkt->hdr + pkt->offset); in bth_tver() [all …]
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/drivers/mtd/parsers/ |
D | bcm47xxpart.c | 51 uint32_t offset[3]; member 55 u64 offset, uint32_t mask_flags) in bcm47xxpart_add_part() argument 58 part->offset = offset; in bcm47xxpart_add_part() 94 uint32_t offset; in bcm47xxpart_parse() local 121 for (offset = 0; offset <= master->size - blocksize; in bcm47xxpart_parse() 122 offset += blocksize) { in bcm47xxpart_parse() 124 if (IS_ENABLED(CONFIG_BCM47XX) && offset >= 0x2000000) in bcm47xxpart_parse() 133 err = mtd_read(master, offset, BCM47XXPART_BYTES_TO_READ, in bcm47xxpart_parse() 137 offset, err); in bcm47xxpart_parse() 145 offset, MTD_WRITEABLE); in bcm47xxpart_parse() [all …]
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/drivers/gpu/host1x/hw/ |
D | host1x02_hardware.h | 33 unsigned indx, unsigned base_indx, unsigned offset) in host1x_class_host_wait_syncpt_base() argument 37 | host1x_uclass_wait_syncpt_base_offset_f(offset); in host1x_class_host_wait_syncpt_base() 41 unsigned base_indx, unsigned offset) in host1x_class_host_incr_syncpt_base() argument 44 | host1x_uclass_incr_syncpt_base_offset_f(offset); in host1x_class_host_incr_syncpt_base() 55 unsigned mod_id, unsigned offset, bool auto_inc) in host1x_class_host_indoff_reg_write() argument 59 | host1x_uclass_indoff_indroffset_f(offset); in host1x_class_host_indoff_reg_write() 66 unsigned mod_id, unsigned offset, bool auto_inc) in host1x_class_host_indoff_reg_read() argument 69 | host1x_uclass_indoff_indroffset_f(offset) in host1x_class_host_indoff_reg_read() 78 unsigned class_id, unsigned offset, unsigned mask) in host1x_opcode_setclass() argument 80 return (0 << 28) | (offset << 16) | (class_id << 6) | mask; in host1x_opcode_setclass() [all …]
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D | host1x04_hardware.h | 33 unsigned indx, unsigned base_indx, unsigned offset) in host1x_class_host_wait_syncpt_base() argument 37 | host1x_uclass_wait_syncpt_base_offset_f(offset); in host1x_class_host_wait_syncpt_base() 41 unsigned base_indx, unsigned offset) in host1x_class_host_incr_syncpt_base() argument 44 | host1x_uclass_incr_syncpt_base_offset_f(offset); in host1x_class_host_incr_syncpt_base() 55 unsigned mod_id, unsigned offset, bool auto_inc) in host1x_class_host_indoff_reg_write() argument 59 | host1x_uclass_indoff_indroffset_f(offset); in host1x_class_host_indoff_reg_write() 66 unsigned mod_id, unsigned offset, bool auto_inc) in host1x_class_host_indoff_reg_read() argument 69 | host1x_uclass_indoff_indroffset_f(offset) in host1x_class_host_indoff_reg_read() 78 unsigned class_id, unsigned offset, unsigned mask) in host1x_opcode_setclass() argument 80 return (0 << 28) | (offset << 16) | (class_id << 6) | mask; in host1x_opcode_setclass() [all …]
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D | host1x05_hardware.h | 33 unsigned indx, unsigned base_indx, unsigned offset) in host1x_class_host_wait_syncpt_base() argument 37 | host1x_uclass_wait_syncpt_base_offset_f(offset); in host1x_class_host_wait_syncpt_base() 41 unsigned base_indx, unsigned offset) in host1x_class_host_incr_syncpt_base() argument 44 | host1x_uclass_incr_syncpt_base_offset_f(offset); in host1x_class_host_incr_syncpt_base() 55 unsigned mod_id, unsigned offset, bool auto_inc) in host1x_class_host_indoff_reg_write() argument 59 | host1x_uclass_indoff_indroffset_f(offset); in host1x_class_host_indoff_reg_write() 66 unsigned mod_id, unsigned offset, bool auto_inc) in host1x_class_host_indoff_reg_read() argument 69 | host1x_uclass_indoff_indroffset_f(offset) in host1x_class_host_indoff_reg_read() 78 unsigned class_id, unsigned offset, unsigned mask) in host1x_opcode_setclass() argument 80 return (0 << 28) | (offset << 16) | (class_id << 6) | mask; in host1x_opcode_setclass() [all …]
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D | host1x01_hardware.h | 33 unsigned indx, unsigned base_indx, unsigned offset) in host1x_class_host_wait_syncpt_base() argument 37 | host1x_uclass_wait_syncpt_base_offset_f(offset); in host1x_class_host_wait_syncpt_base() 41 unsigned base_indx, unsigned offset) in host1x_class_host_incr_syncpt_base() argument 44 | host1x_uclass_incr_syncpt_base_offset_f(offset); in host1x_class_host_incr_syncpt_base() 55 unsigned mod_id, unsigned offset, bool auto_inc) in host1x_class_host_indoff_reg_write() argument 59 | host1x_uclass_indoff_indroffset_f(offset); in host1x_class_host_indoff_reg_write() 66 unsigned mod_id, unsigned offset, bool auto_inc) in host1x_class_host_indoff_reg_read() argument 69 | host1x_uclass_indoff_indroffset_f(offset) in host1x_class_host_indoff_reg_read() 79 unsigned class_id, unsigned offset, unsigned mask) in host1x_opcode_setclass() argument 81 return (0 << 28) | (offset << 16) | (class_id << 6) | mask; in host1x_opcode_setclass() [all …]
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