| /drivers/firmware/ |
| D | arm_scpi.c | 307 } opps[MAX_DVFS_OPPS]; member
637 info->opps = kcalloc(info->count, sizeof(*opp), GFP_KERNEL); in scpi_dvfs_get_info()
638 if (!info->opps) { in scpi_dvfs_get_info()
643 for (i = 0, opp = info->opps; i < info->count; i++, opp++) { in scpi_dvfs_get_info()
644 opp->freq = le32_to_cpu(buf.opps[i].freq); in scpi_dvfs_get_info()
645 opp->m_volt = le32_to_cpu(buf.opps[i].m_volt); in scpi_dvfs_get_info()
648 sort(info->opps, info->count, sizeof(*opp), opp_cmp_func, NULL); in scpi_dvfs_get_info()
694 if (!info->opps) in scpi_dvfs_add_opps_to_device()
697 for (opp = info->opps, idx = 0; idx < info->count; idx++, opp++) { in scpi_dvfs_add_opps_to_device()
871 kfree(info->dvfs[i]->opps); in scpi_remove()
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| /drivers/clk/ |
| D | clk-scpi.c | 67 const struct scpi_opp *opp = clk->info->opps; in __scpi_dvfs_round_rate()
92 opp = clk->info->opps + idx; in scpi_dvfs_recalc_rate()
107 const struct scpi_opp *opp = clk->info->opps; in __scpi_find_dvfs_index()
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 811 if (pool->base.opps[i] != NULL) in dce80_resource_destruct()
812 dce110_opp_destroy(&pool->base.opps[i]); in dce80_resource_destruct()
1078 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce80_construct()
1079 if (pool->base.opps[i] == NULL) { in dce80_construct()
1276 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce81_construct()
1277 if (pool->base.opps[i] == NULL) { in dce81_construct()
1470 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce83_construct()
1471 if (pool->base.opps[i] == NULL) { in dce83_construct()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 806 if (pool->base.opps[i] != NULL) in dce60_resource_destruct()
807 dce110_opp_destroy(&pool->base.opps[i]); in dce60_resource_destruct()
1069 pool->base.opps[i] = dce60_opp_create(ctx, i); in dce60_construct()
1070 if (pool->base.opps[i] == NULL) { in dce60_construct()
1267 pool->base.opps[i] = dce60_opp_create(ctx, i); in dce61_construct()
1268 if (pool->base.opps[i] == NULL) { in dce61_construct()
1461 pool->base.opps[i] = dce60_opp_create(ctx, i); in dce64_construct()
1462 if (pool->base.opps[i] == NULL) { in dce64_construct()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 824 if (pool->base.opps[i] != NULL) in dce110_resource_destruct()
825 dce110_opp_destroy(&pool->base.opps[i]); in dce110_resource_destruct()
1146 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; in dce110_acquire_underlay()
1274 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1477 pool->base.opps[i] = dce110_opp_create(ctx, i); in dce110_resource_construct()
1478 if (pool->base.opps[i] == NULL) { in dce110_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 763 if (pool->base.opps[i] != NULL) in dce100_resource_destruct()
764 dce110_opp_destroy(&pool->base.opps[i]); in dce100_resource_destruct()
1115 pool->base.opps[i] = dce100_opp_create(ctx, i); in dce100_resource_construct()
1116 if (pool->base.opps[i] == NULL) { in dce100_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.c | 301 opp = dc->res_pool->opps[opp_id_src0]; in dcn20_init_blank()
310 bottom_opp = dc->res_pool->opps[opp_id_src1]; in dcn20_init_blank()
1437 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { in dcn20_update_dchubp_dpp()
1439 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; in dcn20_update_dchubp_dpp()
2474 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn20_fpga_init_hw()
2475 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; in dcn20_fpga_init_hw()
2477 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; in dcn20_fpga_init_hw()
2501 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn20_fpga_init_hw()
2502 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; in dcn20_fpga_init_hw()
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| D | dcn20_resource.c | 1514 if (pool->base.opps[i] != NULL) in dcn20_resource_destruct()
1515 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn20_resource_destruct()
1927 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
4044 pool->base.opps[i] = dcn20_opp_create(ctx, i);
4045 if (pool->base.opps[i] == NULL) {
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 987 if (pool->base.opps[i] != NULL) in dcn10_resource_destruct()
988 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn10_resource_destruct()
1585 pool->base.opps[j] = dcn10_opp_create(ctx, i); in dcn10_resource_construct()
1586 if (pool->base.opps[j] == NULL) { in dcn10_resource_construct()
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| D | dcn10_hw_sequencer.c | 355 if (pool->opps[i]->funcs->dpg_is_blanked) in dcn10_log_hw_state()
356 s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]); in dcn10_log_hw_state()
1242 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; in dcn10_init_pipes()
1243 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; in dcn10_init_pipes()
1244 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_init_pipes()
1245 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; in dcn10_init_pipes()
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 609 if (pool->base.opps[i] != NULL) in dce120_resource_destruct()
610 dce110_opp_destroy(&pool->base.opps[i]); in dce120_resource_destruct()
1209 pool->base.opps[j] = dce120_opp_create( in dce120_resource_construct()
1212 if (pool->base.opps[j] == NULL) { in dce120_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 784 if (pool->base.opps[i] != NULL) in dce112_resource_destruct()
785 dce110_opp_destroy(&pool->base.opps[i]); in dce112_resource_destruct()
1360 pool->base.opps[i] = dce112_opp_create( in dce112_resource_construct()
1363 if (pool->base.opps[i] == NULL) { in dce112_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 965 if (pool->base.opps[i] != NULL) in dcn21_resource_destruct()
966 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn21_resource_destruct()
2015 pool->base.opps[j] = dcn21_opp_create(ctx, i); in dcn21_resource_construct()
2016 if (pool->base.opps[j] == NULL) { in dcn21_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 187 struct output_pixel_processor *opps[MAX_PIPES]; member
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1264 if (pool->base.opps[i] != NULL) in dcn30_resource_destruct()
1265 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn30_resource_destruct()
1879 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
2764 pool->base.opps[i] = dcn30_opp_create(ctx, i); in dcn30_resource_construct()
2765 if (pool->base.opps[i] == NULL) { in dcn30_resource_construct()
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| /drivers/mfd/ |
| D | db8500-prcmu.c | 1800 u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP }; in set_armss_rate() local
1824 pr_debug("SET ARM OPP 0x%02x\n", opps[i]); in set_armss_rate()
1825 return db8500_prcmu_set_arm_opp(opps[i]); in set_armss_rate()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_resource.c | 1406 split_pipe->stream_res.opp = pool->opps[i]; in acquire_first_split_pipe()
1784 pipe_ctx->stream_res.opp = pool->opps[i]; in acquire_first_free_pipe()
2040 pipe_ctx->stream_res.opp = pool->opps[tg_inst]; in acquire_resource_from_hw_enabled_state()
|