Searched refs:phy_ctrl_1_shdw (Results 1 – 2 of 2) sorted by relevance
586 u32 phy_ctrl_1_shdw; member
833 writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); in setup_registers()1615 regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d( in get_emif_reg_values()1618 regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl); in get_emif_reg_values()