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Searched refs:pipe_count (Results 1 – 25 of 26) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/core/
Ddc.c788 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_ctx_interdependent_lock()
813 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
855 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
958 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1027 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1030 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1053 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1056 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1063 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1076 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
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Ddc_surface.c150 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
162 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
Ddc_debug.c318 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
330 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
Ddc_resource.c1293 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in find_idle_secondary_pipe()
1305 for (i = pool->pipe_count - 1; i >= 0; i--) { in find_idle_secondary_pipe()
1363 for (i = pool->pipe_count - 1; i >= 0; i--) { in acquire_free_pipe_for_head()
1389 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_split_pipe()
1520 for (i = pool->pipe_count - 1; i >= 0; i--) { in dc_remove_plane_from_context()
1774 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_free_pipe()
2224 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dc_validate_global_state()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer_debug.c133 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_hubp_states()
203 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_rq_states()
248 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_dlg_states()
302 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_ttu_states()
341 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_cm_states()
394 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_mpcc_states()
509 for (i = 0; i < pool->pipe_count; i++) { in dcn10_clear_hubp_underflow()
Ddcn10_hw_sequencer.c94 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
164 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
196 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
221 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
253 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
286 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
328 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
695 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
739 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_bios_golden_init()
766 for (i = 0; i < dc->res_pool->pipe_count; i++) { in false_optc_underflow_wa()
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Ddcn10_resource.c986 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_destruct()
1371 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1374 pool->base.pipe_count = 3; in dcn10_resource_construct()
1554 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_construct()
1623 pool->base.pipe_count = j; in dcn10_resource_construct()
1629 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1630 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1652 dc->caps.max_planes = pool->base.pipe_count; in dcn10_resource_construct()
/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_resource.c810 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
883 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce80_validate_bandwidth()
969 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
1048 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1110 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1168 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1246 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1308 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1366 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1440 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
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/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_resource.c805 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
878 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_validate_bandwidth()
964 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1039 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1101 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1159 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1237 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1299 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1357 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1431 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
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Ddce60_hw_sequencer.c70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_resource.c823 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
986 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1274 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1275 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1276 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1277 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1278 pool->pipe_count++; in underlay_create()
1371 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1372 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1444 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_construct()
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Ddce110_hw_sequencer.c1583 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vga_and_power_gate_all_controllers()
1880 for (i = 0; i < dc->res_pool->pipe_count; i++) { in should_enable_fbc()
1896 if (i == dc->res_pool->pipe_count) in should_enable_fbc()
2043 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
2069 if (i == dc->res_pool->pipe_count) { in dce110_setup_audio_dto()
2070 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
2120 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2145 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2448 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
2476 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
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/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c1483 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_destruct()
1726 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1974 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
2013 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
2033 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2436 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2482 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2552 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2575 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2597 for (i = 0; i < dc->res_pool->pipe_count; i++) {
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Ddcn20_hwseq.c1434 int opp_count = dc->res_pool->pipe_count; in dcn20_update_dchubp_dpp()
1652 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1663 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1676 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1681 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1689 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1700 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1730 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
1740 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_post_unlock_program_front_end()
1825 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_update_bandwidth()
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/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c1233 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1314 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1348 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1350 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1373 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1375 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1457 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1476 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_writeback_from_context()
1593 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1828 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
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Ddcn30_hwseq.c396 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) { in dcn30_program_all_writeback_pipes_in_tree()
613 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_init_hw()
/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_resource.c762 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_destruct()
849 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
1070 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1079 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_construct()
1142 dc->caps.max_planes = pool->base.pipe_count; in dce100_resource_construct()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c934 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_destruct()
1103 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_calculate_wm()
1182 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn21_validate_bandwidth_fp()
1414 dcn2_1_ip.max_num_dpp = pool->base.pipe_count; in update_bw_bounding_box()
1822 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1873 pool->base.pipe_count = 4; in dcn21_resource_construct()
1984 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_construct()
2052 pool->base.pipe_count = j; in dcn21_resource_construct()
2096 dc->caps.max_planes = pool->base.pipe_count; in dcn21_resource_construct()
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_resource.c608 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_destruct()
1078 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1165 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_construct()
1241 pool->base.pipe_count = j; in dce120_resource_construct()
1256 dc->caps.max_planes = pool->base.pipe_count; in dce120_resource_construct()
/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c783 for (i = 0; i < pool->base.pipe_count; i++) { in dce112_resource_destruct()
906 dc->res_pool->pipe_count, in dce112_validate_bandwidth()
1239 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1324 for (i = 0; i < pool->base.pipe_count; i++) { in dce112_resource_construct()
1393 dc->caps.max_planes = pool->base.pipe_count; in dce112_resource_construct()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c166 for (i = 0; i < dc->res_pool->pipe_count; i++) { in ramp_up_dispclk_with_dpp()
/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h208 unsigned int pipe_count; member
Ddce_calcs.h485 int pipe_count,
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c109 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddce_calcs.c2760 const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data) in populate_initial_data() argument
2776 for (i = 0; i < pipe_count; i++) { in populate_initial_data()
2886 for (i = 0; i < pipe_count; i++) { in populate_initial_data()
2982 int pipe_count) in all_displays_in_sync() argument
2987 for (i = 0; i < pipe_count; i++) { in all_displays_in_sync()
3018 int pipe_count, in bw_calcs() argument
3026 populate_initial_data(pipe, pipe_count, data); in bw_calcs()
3029 calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count); in bw_calcs()

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