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Searched refs:pl1 (Results 1 – 3 of 3) sorted by relevance

/drivers/pinctrl/tegra/
Dpinctrl-tegra210.c1510 …PINGROUP(pl1, SOC, RSVD1, RSVD2, RSVD3, 0x3278, Y, Y, N, -1…
1533 DRV_PINGROUP(pl1, 0x9f8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu7_hwmgr.c4296 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1, in smu7_are_power_levels_equal() argument
4299 return ((pl1->memory_clock == pl2->memory_clock) && in smu7_are_power_levels_equal()
4300 (pl1->engine_clock == pl2->engine_clock) && in smu7_are_power_levels_equal()
4301 (pl1->pcie_gen == pl2->pcie_gen) && in smu7_are_power_levels_equal()
4302 (pl1->pcie_lane == pl2->pcie_lane)); in smu7_are_power_levels_equal()
Dvega10_hwmgr.c4807 const struct vega10_performance_level *pl1, in vega10_are_power_levels_equal() argument
4810 return ((pl1->soc_clock == pl2->soc_clock) && in vega10_are_power_levels_equal()
4811 (pl1->gfx_clock == pl2->gfx_clock) && in vega10_are_power_levels_equal()
4812 (pl1->mem_clock == pl2->mem_clock)); in vega10_are_power_levels_equal()