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Searched refs:plane_id (Results 1 – 18 of 18) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_sprite.c346 enum plane_id plane_id) in icl_is_nv12_y_plane() argument
349 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); in icl_is_nv12_y_plane()
352 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) in icl_is_hdr_plane() argument
355 icl_hdr_plane_mask() & BIT(plane_id); in icl_is_hdr_plane()
492 enum plane_id plane_id = plane->id; in icl_program_input_csc() local
534 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), in icl_program_input_csc()
536 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), in icl_program_input_csc()
538 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), in icl_program_input_csc()
540 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), in icl_program_input_csc()
542 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), in icl_program_input_csc()
[all …]
Dintel_sprite.h33 enum pipe pipe, enum plane_id plane_id);
42 enum plane_id plane_id);
43 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
Dintel_atomic_plane.c377 enum plane_id plane_id = plane->id; in skl_next_plane_to_commit() local
380 !(*update_mask & BIT(plane_id))) in skl_next_plane_to_commit()
383 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_next_plane_to_commit()
385 I915_MAX_PLANES, plane_id) || in skl_next_plane_to_commit()
386 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id], in skl_next_plane_to_commit()
388 I915_MAX_PLANES, plane_id)) in skl_next_plane_to_commit()
391 *update_mask &= ~BIT(plane_id); in skl_next_plane_to_commit()
392 entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_next_plane_to_commit()
393 entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id]; in skl_next_plane_to_commit()
Dintel_bw.c275 enum plane_id plane_id; in intel_bw_crtc_data_rate() local
277 for_each_plane_id_on_crtc(crtc, plane_id) { in intel_bw_crtc_data_rate()
282 if (plane_id == PLANE_CURSOR) in intel_bw_crtc_data_rate()
285 data_rate += crtc_state->data_rate[plane_id]; in intel_bw_crtc_data_rate()
380 enum plane_id plane_id; in skl_bw_calc_min_cdclk() local
396 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_bw_calc_min_cdclk()
398 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_bw_calc_min_cdclk()
400 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; in skl_bw_calc_min_cdclk()
401 unsigned int data_rate = crtc_state->data_rate[plane_id]; in skl_bw_calc_min_cdclk()
Dintel_display_debugfs.c1041 enum plane_id plane_id; in i915_ddb_info() local
1045 for_each_plane_id_on_crtc(crtc, plane_id) { in i915_ddb_info()
1046 entry = &crtc_state->wm.skl.plane_ddb_y[plane_id]; in i915_ddb_info()
1047 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, in i915_ddb_info()
Dintel_display.h173 enum plane_id { enum
Dintel_display_types.h1157 enum plane_id id;
Dintel_display.c10542 enum plane_id plane_id = plane->id; in skl_get_initial_plane_config() local
10565 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); in skl_get_initial_plane_config()
10574 PLANE_COLOR_CTL(pipe, plane_id)); in skl_get_initial_plane_config()
10642 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000; in skl_get_initial_plane_config()
10645 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); in skl_get_initial_plane_config()
10647 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); in skl_get_initial_plane_config()
10651 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); in skl_get_initial_plane_config()
/drivers/gpu/drm/i915/
Dintel_pm.c1090 static int g4x_plane_fifo_size(enum plane_id plane_id, int level) in g4x_plane_fifo_size() argument
1106 switch (plane_id) { in g4x_plane_fifo_size()
1114 MISSING_CASE(plane_id); in g4x_plane_fifo_size()
1194 int level, enum plane_id plane_id, u16 value) in g4x_raw_plane_wm_set() argument
1202 dirty |= raw->plane[plane_id] != value; in g4x_raw_plane_wm_set()
1203 raw->plane[plane_id] = value; in g4x_raw_plane_wm_set()
1238 enum plane_id plane_id = plane->id; in g4x_raw_plane_wm_compute() local
1243 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0); in g4x_raw_plane_wm_compute()
1244 if (plane_id == PLANE_PRIMARY) in g4x_raw_plane_wm_compute()
1254 max_wm = g4x_plane_fifo_size(plane_id, level); in g4x_raw_plane_wm_compute()
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Di915_reg.h6829 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ argument
6830 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6831 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ argument
6832 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
6834 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) argument
6835 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) argument
6836 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) argument
6837 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) argument
6838 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) argument
6839 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) argument
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Di915_drv.h1278 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ argument
1281 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
/drivers/gpu/drm/sti/
Dsti_mixer.c239 int plane_id, depth = plane->drm_plane.state->normalized_zpos; in sti_mixer_set_plane_depth() local
245 plane_id = GAM_DEPTH_GDP0_ID; in sti_mixer_set_plane_depth()
248 plane_id = GAM_DEPTH_GDP1_ID; in sti_mixer_set_plane_depth()
251 plane_id = GAM_DEPTH_GDP2_ID; in sti_mixer_set_plane_depth()
254 plane_id = GAM_DEPTH_GDP3_ID; in sti_mixer_set_plane_depth()
257 plane_id = GAM_DEPTH_VID0_ID; in sti_mixer_set_plane_depth()
271 if ((val & mask) == plane_id << (3 * i)) in sti_mixer_set_plane_depth()
276 plane_id = plane_id << (3 * depth); in sti_mixer_set_plane_depth()
281 plane_id, mask); in sti_mixer_set_plane_depth()
284 val |= plane_id; in sti_mixer_set_plane_depth()
/drivers/gpu/drm/i915/gvt/
Ddmabuf.c267 int plane_id) in vgpu_get_plane_info() argument
275 if (plane_id == DRM_PLANE_TYPE_PRIMARY) { in vgpu_get_plane_info()
305 } else if (plane_id == DRM_PLANE_TYPE_CURSOR) { in vgpu_get_plane_info()
327 gvt_vgpu_err("invalid plane id:%d\n", plane_id); in vgpu_get_plane_info()
Dhandlers.c803 enum plane_id plane = REG_50080_TO_PLANE(offset); in reg50080_mmio_write()
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_trace.h641 TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
645 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp,
649 __field( uint32_t, plane_id )
663 __entry->plane_id = plane_id;
679 __entry->crtc_id, __entry->plane_id, __entry->fb_id,
/drivers/gpu/drm/
Ddrm_plane.c532 plane = drm_plane_find(dev, file_priv, plane_resp->plane_id); in drm_mode_getplane()
552 plane_resp->plane_id = plane->base.id; in drm_mode_getplane()
816 plane = drm_plane_find(dev, file_priv, plane_req->plane_id); in drm_mode_setplane()
819 plane_req->plane_id); in drm_mode_setplane()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c643 int plane_id) in power_on_plane() argument
651 hws->funcs.dpp_pg_control(hws, plane_id, true); in power_on_plane()
654 hws->funcs.hubp_pg_control(hws, plane_id, true); in power_on_plane()
659 "Un-gated front end for pipe %d\n", plane_id); in power_on_plane()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.c3249 struct amdgpu_mode_info *mode_info, int plane_id, in initialize_plane() argument
3270 possible_crtcs = 1 << plane_id; in initialize_plane()
3271 if (plane_id >= dm->dc->caps.max_streams) in initialize_plane()
3283 mode_info->planes[plane_id] = plane; in initialize_plane()